## 文献概述

AbstractContent
TitleHigh-performance ultra-compact polarization splitter rotators based on dual-etching and tapered asymmetrical directional coupler
Published2021-9-13
PlatformSilicon
Functionthe incident light with orthogonal polarization (TE0 & TM0) can be separated and rotated on one of them (TM0 to TE0).
Footprinta total length of ~28μm
Resultmode extinction ratio is higher than 28 dB or 32 dB @1550 nm for the launched fundamental transverse magnetic or the transverse electric modes, while the corresponding insertion loss and polarization conversion loss are 0.33 dB and 0.18 dB.
an ER of more than 20 or 28 dB over 1510–1580 nm for TE0 or TM0 modes. For a launched TE0 mode, the insertion loss (IL) is less than 0.6 dB within the 70 nm bandwidth. For a launched TM0 mode, the polarization conversion loss (PCL) is less than 1 or 3 dB within the bandwidth of 45 or 70 nm, respectively.
PDFhere

## 笔记

### 1. Introduction

Photonic integrated circuits (PICs) fabricated in the silicon-on-insulator (SOI) platform are essential for massive applications in communications, military, and sensing. Due to its CMOS compatibility and ultra-high index contrast in the SOI platform, the PICs can be fabricated with low cost and compact footprint[1][2][3][4] .

Polarization splitter-rotators (PSRs) are one of the key components in PICs to overcome the highly polarization-dependent issue brought by the silicon waveguide.

Typically, the PSR combines the functions of the polarization beam splitter (PBS) and polarization rotators (PRs), so the incident light with orthogonal polarization can be separated and rotated on one of them.

Thus, the PSRs are widely used to meet significant requirements for polarization processing and multiplexing. Recently, various PSRs have been proposed with different structures, such as the mode-sorting asymmetric Y-junction[5][6] , multimode interferometer[7][8] , and asymmetric directional coupler (ADC)[9][10] .

Among them, the PSRs fabricated by the ADC structure have advantages on performance, footprint, and design flexibility. However, this type of PSR is sensitive to fabrication errors. To address this problem, several novel concepts have been incorporated into the ADC structures, such as subwavelength grating (SWG), hybrid plasmonic waveguide, and quasi-adiabatic couplers… However, the hybrid plasmonic is complicated to realize under current commercial tape-out processing conditions(流片).

### 2. Design

The top cladding of the PSR is specified as air to achieve a more compact footprint (the reason can be explained in this paper).

“ The through-port waveguides of two PSRs are both dual etched. The first stage is partially etched, and a tapered coupler is formed in the coupling region. An S-bend section is used to decouple at the end of the coupling region. Meanwhile, the etching width remains unchanged until arriving at the end of the S-bend. Then, the etched width is gradually increased, and it finally forms a full etching. Right now, the waveguide supports a single mode, and only the TE0 mode can be guided in this port. A reverse taper is used to recover the waveguide thickness. The cross-port waveguide might be an SWG or a nanowire, as shown in Figs. 1(a) and 1(b). ”

### 3. Fabrication

A standard SOI wafer, has a 220 nm silicon layer and a 3 μm SiO2 substrate. Therefore, the whole height of core layer is 220 nm out of consideration for the fabrication process.

We designed two vertical coupling gratings for supporting the TE0 and TM0 modes, respectively. The period and filling factor of the TE0 grating coupler are designed as 620 nm and 45%, while 1050 nm and 47% are for the corresponding TM0 grating coupler.

### 4. Measurement

During the performance tests, several TE0–TE0 and TM0–TM0 reference waveguides are fabricated, and their transmission responses are shown in Fig. 7. It can be found that coupling losses of TE0 and TM0 grating couplers are 7.7 dB/port and 11.4 dB/port at the center wavelength, respectively.

The experiment and simulation results for PSRs are shown in Fig. 8, after being calibrated with the reference waveguide. The IL of the TE0 mode in through port is less than 0.6 dB within the bandwidth of 1510–1580 nm, while the ER is higher than 20 dB. The TM0–TE0 conversion efficiency reaches the maximum of 96% at λ = 1550 nm, with a PCL of 0.18 dB. In the 1535–1580 nm range, the PCL is less than 1 dB, and the ER is larger than 28 dB. （这里我比较疑惑PCL是怎么计算的

## 参考文献

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Author     : Hao Zhang (张豪)